{"id":"CVE-2019-0124","revision":"8e58f9f388e64e03ae9d15ab85f74229","records":[{"revision":"8e58f9f388e64e03ae9d15ab85f74229","observedAt":"2026-10-23T15:48:27.903+00:00","statement":{"source":"cve-program","id":"CVE-2019-0124","aliases":[],"title":"Insufficient memory protection in Intel(R) 6th Generation Core Processors and greater, supporting TXT, may allow a privileged user to potentially enable escalation of privilege via local access.","description":"Insufficient memory protection in Intel(R) 6th Generation Core Processors and greater, supporting TXT, may allow a privileged user to potentially enable escalation of privilege via local access.","state":0,"publishedAt":"2019-11-14T19:07:54+00:00","modifiedAt":"2026-10-08T21:03:15.477+00:00","affected":[{"ecosystem":"Vendor product","name":"2019.2 IPU – Intel(R) SGX and TXT","ranges":[],"versions":[],"rawVersionEvidence":"{\n                    \"product\": \"2019.2 IPU – Intel(R) SGX and TXT\",\n                    \"vendor\": \"n/a\",\n                    \"versions\": [\n                        {\n                            \"status\": \"affected\",\n                            \"version\": \"See provided reference\"\n                        }\n                    ]\n                }"}],"metrics":[],"references":["https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00220.html","https://support.f5.com/csp/article/K81556107?utm_source=f5support&amp%3Butm_medium=RSS"],"sourceUrl":"https://www.cve.org/CVERecord?id=CVE-2019-0124","license":"CVE Program Terms of Use","key":"cve-program:CVE-2019-0124","identifiers":["CVE-2019-0124"]},"retained":false,"historicalAffected":[]}],"coverage":[]}