CVE-2024-42279Published

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

Exact source revision recorded 30 Oct 2026 13:45:33 UTC. It does not establish the source's current position. Latest evidence.

Recorded JSON

cve-program · CVE-2024-42279

Published

In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.

Source published: 17 Aug 2024 09:08:46 UTC
Source modified: 30 Oct 2026 12:19:01 UTC
Observed here: 30 Oct 2026 13:45:33 UTC
Source terms: CVE Program Terms of Use

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CVSS 3.1 · 7.8 CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H