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irqchip/gic-v5: Immediately exec priority drop following activate

Assessment

Severity
Moderate
CVSS base score
5.5CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H
Impact
Not stated
EPSS, next 30 days
Not scored yet
Public exploit code
No Nuclei template lists it
Exploitability
Not assessed
Publicly disclosed
No
Customer action
Required: apply the update
Component
Mariner
Weakness
—
Issued by
Linux
Published
24 Oct 2026 · October 2026
Last revised
24 Oct 2026
CVSS 3.1 base metricsRed raises the risk · green lowers it
Attack vector
LocalAV:L
Attack complexity
LowAC:L
Privileges required
LowPR:L
User interaction
NoneUI:N
Scope
UnchangedS:U
Confidentiality
NoneC:N
Integrity
NoneI:N
Availability
HighA:H

Updates that fix it

0 KBs

No KB listed

MSRC lists no downloadable update, which usually means a service-side fix or a release-notes update. Check the MSRC advisory.

Affected products

1 affected product
  • azl3 kernel 6.6.157.1-1 on Azure Linux 3.0
Page history

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Field-level log (0)

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No retained field changes for this selection.

Explore global source statements, affected packages and advisory history for CVE-2026-98878. The catalog has a separate collection scope from Microsoft release records.

Collected exploitation and prediction evidence

Risk source coverage

CISA KEV is observed exploitation evidence. FIRST EPSS is a dated prediction of exploitation in the next 30 days. Missing scores are unknown. This collector requests predictions only for explicit CVE aliases in the public NuGet archive; Microsoft release views retain their existing prediction scope.

No collected risk observation for these identifiers. This does not establish absence of exploitation or a zero probability.

cve-program · CVE-2026-98878

Published

irqchip/gic-v5: Immediately exec priority drop following activate

In the Linux kernel, the following vulnerability has been resolved: irqchip/gic-v5: Immediately exec priority drop following activate With GICv5 an interrupt of equal or lower priority cannot be signalled until there has been a priority drop. This is done via the GIC CDEOI system instruction. Once this has been executed, the hardware is able to signal the next interrupt if there is one. As all interrupts are programmed to have the same priority, no new interrupts can be signalled until the priority drop has happened. This can cause issues when, for example, an interrupt remains active while a long running process takes place, such as when injecting a physical interrupt into a guest VM in software. The GICv5 driver has so far done the priority drop as part of irq_eoi(), i.e., at the same time as deactivating the interrupt. This means that any long running process (or VM) could block incoming interrupts, effectively causing a denial of service for all other interrupts. Rather than doing the EOI as part of irq_eoi() (which the name would suggest would be a good place for it), move it to happen immediately after acknowledging an interrupt in the main GICv5 interrupt handler. The deactivation of interrupts (GIC CDDI) remains implemented as part of irq_eoi(), which means that the same interrupt cannot be signalled a second time until deactivated by software.

Source published
23 Oct 2026 11:37:25 UTC
Source modified
26 Oct 2026 06:56:00 UTC
Observed here
26 Oct 2026 08:20:49 UTC
Source terms
CVE Program Terms of Use

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